LogicIR: Logic Gate Networks for Image Restoration¶

Conference: ECCV2026
arXiv: 2606.26609
Code: https://github.com/jimmy9704/LogicIR
Area: Image Restoration / Model Compression
Keywords: Logic Gate Networks, Image Restoration, Binary Neural Networks, Lightweight Inference, Bit Decoding

TL;DR¶

LogicIR is the first logic gate network (LGN) specifically designed for image restoration. Through a fully logic-gate UNet architecture, a differentiable bit decoding layer, and an Index Shuffling cross-group communication mechanism, it achieves competitive restoration quality on denoising, deblocking, and deraining tasks with operations (BOPs) far lower than BNN and LUT methods, demonstrating the feasibility of pure logic gate operations in image restoration.

Background & Motivation¶

Image restoration (denoising, deblocking, deblurring, deraining) is a core task in low-level vision. Although deep learning methods (DnCNN, SwinIR, Restormer) have pushed restoration quality to high levels, their computational overhead from floating-point multiply-accumulate operations is enormous—processing a 1280x720 image with SwinIR requires approximately 21 Tera floating-point operations, making deployment to resource-constrained scenarios like mobile phones, wearable devices, and embedded systems extremely difficult.

There are two major existing lightweight pipelines, each with fundamental limitations. The Binary Neural Network (BNN) pipeline (BBCU, Bi-Real, ReActNet) binarizes weights and activations to replace multiplications, but the additions in the input/output layers and residual connections still rely on full-precision calculations, and a large number of trainable weight parameters must still be stored—the fully binarized BBCU-lite-fully suffers from severe performance drops (denoising on BSD68 drops from 27.62 dB to 25.23 dB). The Lookup Table (LUT) pipeline (SR-LUT, HKLUT, TinyLUT) pre-stores the input-output mappings of small receptive field networks as lookup tables to accelerate inference, but the table size grows exponentially with the receptive field, restricting the practical receptive field to around 5x5, which fails to capture long-range dependencies and global structures.

Key Challenge: Existing lightweight methods cannot achieve both "pure logic deployability" and "restoration quality". BNNs reduce multiplication but retain addition and weight storage, while LUTs are fast but suffer from structural limitations in their receptive fields; neither achieves the ultimate lightweight goal of "zero arithmetic operations and zero trainable weights".

Logic Gate Networks (LGN) are an emerging paradigm in recent years: inference is completely executed by 16 discrete logic gates such as AND, NAND, and XOR, requiring no trainable weights or floating-point operations, enabling extremely low power consumption and high throughput on FPGAs/ASICs. DiffLogic introduced differentiable relaxation to make LGNs end-to-end trainable, and Convolutional LGN (CLGN) further introduced convolutional logic layers to capture spatial structures. However, LGNs were previously only used for classification tasks, lacking the hierarchical representation, pixel value reconstruction, and long-range spatial modeling capabilities required for image restoration—directly stacking convolutional logic layers (StackedCLGN) for denoising yields only 17.19 dB PSNR, far below the lightest CNN.

Key Insight: This work introduces the LGN paradigm to image restoration for the first time. The core challenges lie in building a UNet-style hierarchical encoder-decoder using pure logic gates, and reconstructing continuous pixel values from binary logic outputs.

Core Idea: A fully logic-gate UNet provides hierarchical feature extraction, differentiable bit decoding maps multi-channel binary outputs to continuous residuals, and Index Shuffling breaks channel isolation in grouped logic layers. These three components work synergistically to bring pure logic gate computation to a practical level for image restoration for the first time.

Method¶

Overall Architecture¶

The core problem LogicIR aims to solve is how to enable a network entirely composed of discrete logic gates to perform hierarchical feature extraction and multi-scale fusion like a CNN UNet, while reconstructing continuous pixel value residuals from naturally binary outputs. The overall pipeline consists of three stages: the input image is first converted into an 8-channel binary representation via bit-plane decomposition; it then passes through a UNet-style encoder-decoder composed of convolutional logic layers to extract hierarchical features, where downsampling uses pixel unshuffle, upsampling uses pixel shuffle, and skip connections use channel concatenation (to avoid addition operations); finally, a bit decoding module maps the multi-channel binary output to a continuous residual in the range of [-1, 1], which is multiplied by a learnable scaling factor and added to the degraded input to obtain the restored result.

%%{init: {'flowchart': {'rankSpacing': 24, 'nodeSpacing': 28, 'padding': 6, 'wrappingWidth': 400}}}%%
flowchart TD
    A["Input I_LQ<br/>H×W Grayscale Image"] --> B["Bit-plane Decomposition<br/>8×H×W Binary Tensor"]
    B --> C["UNet Encoder<br/>Conv Logic 3×3 + 1×1<br/>+ Pixel Unshuffle ↓2"]
    C --> D["Bottleneck<br/>Conv Logic Layers"]
    D --> E["UNet Decoder<br/>Pixel Shuffle ↑2 + Concat Skip Connection<br/>+ Conv Logic 3×3 + 1×1"]
    E --> F["Bit Decoding<br/>C-channel Binary Output<br/>→ bitcount Norm → ×α"]
    F --> G["Residual R<br/>∈[-α, α]"]
    G --> H["Output I_HQ = I_LQ + R"]

Key Designs¶

1. Differentiable Bit Decoding: A Bridge from Binary Activations to Continuous Pixel Values

The output of each layer in an LGN is naturally binary {0, 1}, but image restoration requires continuous pixel value residuals. The most direct approach is to have the network output exactly 8 channels corresponding to 8 bit planes and reconstruct them directly back to 0-255 pixel values—but this is completely unfeasible in practice: low-order bit planes (e.g., bit 0-3) are highly noisy and lack semantic consistency, which drowns out gradient propagation signals during backpropagation, preventing the network from learning effectively. LogicIR's approach is to let the UNet decoder output far more than 8 binary channels (denoted as C, e.g., C=2048), and then convert them into a continuous residual via a simple bitcount normalization operation:

\[\mathbf{\bar{R}}(i,j) = \frac{\sum_{c=0}^{C-1} \mathbf{A}(c,i,j) - 0.5C}{0.5C}\]

where \(\mathbf{A} \in \{0,1\}^{C \times H \times W}\) is the binary activation map finally output by the decoder. This formula maps the "voting" results of C channels to \([-1, 1]\): outputting -1 when all are 0, +1 when all are 1, and 0 when half are 1. Compared to directly learning 8 bit planes, this "majority voting" mechanism is much more robust to noise in individual channels—even if some channels are erroneous, the gradient remains meaningful as long as the majority of channels are correct.

To further increase the representation range, a learnable scaling factor \(\alpha\) is introduced, yielding the final residual \(\mathbf{R} = \alpha \mathbf{\bar{R}}\). Here, \(\alpha\) is optimized alongside the network during the STE fine-tuning stage to adaptively fit the requirements of the task. The elegance of this design lies in the fact that bitcount itself is a pure integer operation (counting the number of 1s), which is extremely cheap in hardware, while \(\alpha\) is merely a scalar multiplication that introduces no substantial overhead during inference.

2. UNet-style Fully Logic-Gate Architecture: Avoiding Additions and Retaining Spatial Information

Directly stacking convolutional logic layers serially (StackedCLGN) for image restoration yields very poor performance (PSNR of only 17.19 dB) because it lacks three critical capabilities: hierarchical feature representation, cross-scale information preservation, and pixel reconstruction. LogicIR designs a complete UNet-style encoder-decoder entirely composed of convolutional logic layers, each with a logic tree depth of d=3, and deliberately avoids traditional addition operations in CNN UNets:

Skip connections use channel concatenation instead of addition: Traditional residual blocks use addition to fuse skip connections and main-path features, but addition requires extra full-adder circuits in pure logic-gate hardware. LogicIR replaces this with channel concatenation, achieving zero-arithmetic-operation feature fusion while preserving the propagation path of high-frequency details.
Downsampling uses pixel unshuffle, upsampling uses pixel shuffle: Traditional UNets use max pooling (requiring comparators) and transposed convolutions (yielding multiply-accumulates). LogicIR replaces these with pixel unshuffle (\(C \times H \times W \rightarrow Cr^2 \times H/r \times W/r\), r=2) and pixel shuffle. These two operations are essentially tensor rearrangements, which can be implemented at zero cost at the logic gate level and preserve spatial information better than pooling.
Residual learning: Following common practices in works like DnCNN, LogicIR learns the residual image \(\mathbf{R}\) rather than directly reconstructing the clean image. The final output is \(\mathbf{\hat{I}}_{HQ} = \mathbf{I}_{LQ} + \mathbf{R}\). Note that the addition here occurs in the floating-point pixel domain (both the input and residual have been converted back to continuous values), which does not affect the pure logic nature of the logic-gate portion of the network.

3. Index Shuffling: Breaking Channel Isolation in Grouped Logic Layers

The working principle of the convolutional logic layer is that each output channel corresponds to a logic tree kernel, whose inputs are randomly sampled from local receptive fields of the input activation map. CLGN introduces a grouping constraint—dividing the input channels evenly into G groups and forcing each logic tree kernel to sample only from its own group—to introduce structured randomness. However, this brings a new issue: the groups are completely isolated from each other, with each group degenerating into an independent sub-network, impeding cross-group information flow. Experiments show that fixed grouping quickly saturates as the layer depth increases, and stacking more layers yields almost no further gain.

Inspired by ShuffleNet, LogicIR proposes Index Shuffling: input channels are still divided into G groups (\(G = C_{in} / 2^d\), where d is the logic tree depth), but each output channel is no longer fixedly bound to a single group. Instead, it selects the input group in a round-robin manner:

\[\mathbf{A}_{out}(n,:,:) = \mathcal{F}^{(n)}(\mathbf{A}_{in}^{g_{cyc}}), \quad g_{cyc} = n \bmod G\]

where \(\mathcal{F}^{(n)}\) is the logic tree kernel of the n-th output channel. This means that adjacent output channels will sequentially select features from different input groups. After accumulating across multiple layers, information from any two groups can interact indirectly. Experiments show (Figs. 11-13) that features are significantly richer after adding Index Shuffling, and "information islands" no longer appear between groups; in terms of PSNR, adding Index Shuffling on top of StackedCLGN improves performance from 27.15 dB to 27.58 dB (+0.43 dB). The elegance of this design lies in the fact that it adds zero computational overhead—it merely alters the input index assignment rules during the wiring stage.

4. MSB Auxiliary Supervision + STE Fine-tuning + Rotational Ensemble: Three Complementary Training Strategies

These three training techniques address different challenges of using LGNs for image restoration:

MSB auxiliary loss targets the information asymmetry among bit planes. The pixel value information of an 8-bit image is highly concentrated in the most significant 4 bits (MSB), whereas the least significant 4 bits (LSB) are dominated by noise-level details. The MSB loss uses a reference image \(\mathbf{\tilde{I}}_{HQ}\) (reconstructed using only the top 4 bit planes of the ground truth image) to calculate the L2 distance with the predicted output for auxiliary supervision: \(\mathcal{L}_{\text{MSB}} = \|\mathbf{\tilde{I}}_{HQ} - \mathbf{\hat{I}}_{HQ}\|_2\). The total loss is \(\mathcal{L}_{\text{total}} = \mathcal{L}_2 + \lambda \mathcal{L}_{\text{MSB}}\). This enables the network to prioritize learning structural outlines in the early stages of training before fine-tuning texture details, preventing gradient disturbance from LSB noise. In ablation studies, the MSB loss yields a +0.14 dB gain.

STE fine-tuning resolves training-inference inconsistency. DiffLogic uses a soft weighting of 16 logic operations (softmax probability weighted sum) during training, but hard-selects the operation with the highest probability during inference (argmax). This mismatch degrades performance. LogicIR appends an STE fine-tuning stage after the main training phase: the forward pass uses the hard-selected discrete gates, while backpropagation still calculates gradients via soft-weighting, allowing the network to gradually adapt to discrete inference while maintaining differentiable training. The learnable scaling factor \(\alpha\) is also optimized during this stage.

Rotational ensemble alleviates insufficient receptive field coverage of random connections. Since the input connections of the logic tree kernels are randomly initialized and fixed during training, each kernel has limited exposure to patterns within its receptive field. The rotational ensemble applies multi-angle rotations (using 2 or 4 angles, i.e., 2RT/4RT) to the input image during inference, performing independent inference, and then inversely rotating and averaging the outputs. Correspondingly, a fine-tuning stage with rotation augmentation is added during training. 4RT improves PSNR by about 0.3 dB compared to single inference, at the cost of multiplying the computational complexity by the number of rotations.

A Complete Example: Forward Pass of a 48x48 Noisy Patch¶

Taking a 48x48 noisy grayscale patch (\(\sigma=25\)) from the BSD68 dataset as an example, the inference pipeline of LogicIR-S is as follows:

Bit-plane Decomposition: The 48x48 8-bit grayscale image is expanded into 8 binary planes \(\mathbf{B}_{LQ} \in \{0,1\}^{8 \times 48 \times 48}\), each corresponding to a bit (from bit7 to bit0).
Encoder Stage: The first layer is a 1x1 convolutional logic layer (capturing channel dependencies), followed by a group of 3x3 + 1x1 convolutional logic layers to extract spatial features. Pixel unshuffle then rearranges the feature maps from \(C \times 48 \times 48\) to \(4C \times 24 \times 24\) (halving spatial resolution and quadrupling channel count). This process is repeated several times, reducing spatial resolution to 12x12 and 6x6, with the channel count growing accordingly.
Bottleneck & Decoder Stage: After processing through several convolutional logic layers at the deepest level, the decoder progressively restores spatial resolution via pixel shuffle: \(C \times 6 \times 6 \rightarrow C/4 \times 12 \times 12\), concatenating channels with the corresponding feature maps from the encoder (skip connections), and fusing them via 3x3 + 1x1 convolutional logic layers, eventually restoring the dimension to 48x48.
Bit Decoding: The decoder finally outputs a binary activation map of \(\mathbf{A} \in \{0,1\}^{2048 \times 48 \times 48}\). The bitcount operation counts the ratio of ones among the 2048 channels at each spatial position, normalizing it to [-1, 1] to obtain \(\mathbf{\bar{R}} \in [-1, 1]^{48 \times 48}\). Multiplying by the learnable \(\alpha\) (approximately 40-50 after training) yields the residual \(\mathbf{R} \in [-50, 50]^{48 \times 48}\).
Output: \(\mathbf{\hat{I}}_{HQ} = \mathbf{I}_{LQ} + \mathbf{R}\) provides the denoised result. Throughout this entire pipeline, steps 1-4 require absolutely no floating-point multiply-accumulates—only step 5 (the final residual addition) involves a single floating-point addition, which occurs in the pixel domain rather than inside the network.

Loss & Training¶

The total loss is \(\mathcal{L}_{\text{total}} = \mathcal{L}_2 + \lambda \mathcal{L}_{\text{MSB}}\), where \(\mathcal{L}_2 = \|\mathbf{I}_{HQ} - \mathbf{\hat{I}}_{HQ}\|_2\) is the primary reconstruction loss, and \(\mathcal{L}_{\text{MSB}} = \|\mathbf{\tilde{I}}_{HQ} - \mathbf{\hat{I}}_{HQ}\|_2\) is the MSB auxiliary loss (\(\mathbf{\tilde{I}}_{HQ}\) is reconstructed using only the top 4 bit planes of the ground truth). Training consists of two stages: the main stage utilizes standard differentiable relaxation (soft logic gate selection) with the Adam optimizer and a learning rate of \(10^{-2}\) for \(8 \times 10^4\) iterations; the STE fine-tuning stage employs hard logic gate forward passes + soft gradient backpropagation, while optimizing the scaling factor \(\alpha\). The rotational ensemble variants undergo additional rotation-augmented training on top of this. Denoising models are trained on 400 grayscale images from the BSD dataset; deblocking and deraining models are initialized from the denoising pre-trained weights.

Key Experimental Results¶

Main Results¶

The table below summarizes the core comparison for grayscale image denoising (\(\sigma=25\)) and JPEG deblocking (\(q=10\)). BOPs are measured on a 1280x720 input. LogicIR-S achieves a denoising PSNR of 27.40 dB on BSD68 with 41.4 G BOPs, which is only 8.3% of HKLUT's operations; the 4RT rotational ensemble version reaches 27.71 dB with 169.3 G BOPs, outperforming BBCU-lite (27.62 dB) with only 15.4% of its computation.

Method	Type	BOPs (Denoising)	BSD68	Set12	Urban100	BOPs (Deblocking)	LIVE1	Classic5
DnCNN-lite	FP	36.6 T	28.24	29.05	27.73	36.6 T	28.78	28.89
BBCU-lite	BNN	1097.2 G	27.62	28.22	26.84	1097.2 G	28.43	28.57
BBCU-lite-fully	BNN	700.6 G	25.23	25.39	24.81	700.6 G	28.13	28.27
HKLUT	LUT	499.4 G	27.34	27.94	26.30	502.7 G	28.54	28.65
TinyLUT	LUT	729.8 G	27.48	28.26	26.42	715.4 G	28.52	28.63
LogicIR-S	Logic	41.4 G	27.40	27.83	26.57	45.2 G	28.48	28.52
LogicIR-S-4RT	Logic	169.3 G	27.71	28.22	26.85	184.6 G	28.62	28.66

On the deraining task (Test100), LogicIR-S achieves 22.75 dB PSNR with 92.7 G BOPs, matching HKLUT (1151.2 G BOPs, 22.71 dB) with only 8.1% of its operation count; LogicIR-S-4RT reaches 22.95 dB with 381.9 G BOPs, outperforming all BNN baselines.

Ablation Study¶

A step-by-step component accumulation experiment (Grayscale denoising on BSD68, without rotational ensemble) clearly demonstrates the contributions of each module. StackedCLGN as the baseline yields only 17.19 dB; bit decoding provides the largest single performance leap (+9.64 dB), demonstrating that the correct conversion from binary to continuous is the primary bottleneck for LGNs in image restoration. The UNet backbone and Index Shuffling provide complementary increments of ~0.3-0.4 dB—the former offers hierarchical representations, while the latter bridges cross-group information flows. The MSB loss and STE fine-tuning supply the final fine-tuning gains of ~0.25 dB.

Configuration	PSNR (dB)	Bit decoding	UNet	Index shuffling	MSB loss	STE fine-tuning
StackedCLGN	17.19
+ Bit decoding	26.83	Y
+ UNet backbone	27.15	Y	Y
+ Index shuffling	27.58	Y	Y	Y
+ MSB loss	27.72	Y	Y	Y	Y
LogicIR-S (full)	27.83	Y	Y	Y	Y	Y

Key Findings¶

Bit decoding is the biggest bottleneck breakthrough point: Adding bit decoding on top of StackedCLGN dramatically boosts PSNR by 9.64 dB, far exceeding the gains of any other single module. This indicates that for LGNs, "how to return to the continuous pixel space from a binary world" is a more fundamental challenge than "how to extract good features".
The gains of Index Shuffling amplify as the network depth increases: The performance gap between fixed grouping and Index Shuffling is small in shallow layers, but widens rapidly with increased layers (as shown in Fig. 12) because fixed grouping accumulates information isolation as depth increases, while Index Shuffling ensures continuous flow of cross-group information.
The cost difference between fully binarizing versus partially binarizing is huge: BBCU-lite retains full-precision first and last layers to yield 27.62 dB PSNR, but binarizing these layers reduces it to 25.23 dB (-2.39 dB). LogicIR is naturally fully binarized, avoiding this performance drop and making it more suitable for pure logic hardware deployment.
Hardware measurements validate real-world speedups: On an Intel Cyclone V C9 FPGA, LogicIR-S takes only 28.2 ms to complete inference, which is 20.3x faster than BBCU-lite (571.6 ms) and 2.5x faster than HKLUT (71.2 ms); its energy consumption is 0.03 mJ compared to 0.69 mJ for BBCU-lite; and its chip area is 0.09 mm^2 (TSMC N5 process) compared to 1.11 mm^2 for HKLUT.

Highlights & Insights¶

The bitcount normalization design is highly elegant: Using 'the statistic of the ratio of ones in C binary channels' to replace directly learning 8 bit planes essentially relaxes 'exact bit assignment' to 'majority voting'. Combined with the learnable scaling factor \(\alpha\), this significantly lowers learning difficulty while maintaining fully binary inference. This approach (approximating continuous values with statistics of redundant binary channels) can be extended to any task requiring continuous values from binary network outputs, such as depth estimation and optical flow prediction.
Systematic design that deliberately avoids addition operations: Every design choice in the UNet architecture—using concat instead of addition for skip connections, using pixel shuffle/unshuffle instead of pooling/transposed convolution for up/downsampling—aims to keep internal operations arithmetic-free. This 'first-principles' design philosophy of constantly questioning the necessity of addition operations is highly instructive.
'Zero-cost information exchange' of Index Shuffling: Simple changing wiring indexes without adding any computation effectively breaks grouping isolation. Similar concepts can be extended to any network structures with random connections and grouping constraints (e.g., randomly connected graph networks, expert assignment in sparse MoE).
Rotational ensemble as a low-cost means to compensate for insufficient receptive field coverage of random connections: Randomly fixed receptive field connections limit each kernel's exposure to patterns. The rotational ensemble utilizes multi-angle inputs to effectively expand the equivalent receptive field coverage, stably gaining about 0.3 dB without changing the network structure. This is applicable to any network with randomly fixed connection structures.

Limitations & Future Work¶

Supports only same-resolution tasks: Currently, LogicIR can only handle restoration tasks where input and output resolutions are identical (denoising, deblocking, deraining), and cannot be directly applied to tasks requiring explicit upsampling such as super-resolution. The authors also point out that designing high-quality upsampling mechanisms within a pure logic-gate framework remains an open challenge.
Computational cost of rotational ensemble: 4RT quadruples the operation count (from 41.4 G to 169.3 G BOPs). Although this is still far lower than BNN/LUT baselines, this linear scaling remains challenging for real-time applications. Whether rotation-invariant constraints can be introduced during training to reduce the number of rotations during inference warrants exploration.
Training costs are not fully discussed: The soft-selection training of LGNs requires maintaining a 16-dimensional probability distribution for each logic gate, and the memory and training time compared to equivalent CNNs are not quantified. Furthermore, the training consists of multiple stages (main training + STE fine-tuning + rotation fine-tuning), making the overall pipeline complex.
Limited to fixed bit-depth grayscale/independent channel processing: LogicIR assumes 8-bit inputs, making expansion to HDR (10/12/16-bit) images non-trivial. Color images are processed with R/G/B channels independently, which fails to exploit inter-channel correlations and may sacrifice color consistency.
Insufficient scalability validation: FPGA experiments were only tested with 64-256 channel width variants on the Intel Cyclone V C9 (low-end FPGA). Resource utilization and timing closure for larger scales (e.g., 4096 channels in the L variant) on high-end FPGAs/ASICs remain unverified.

vs DiffLogic / CLGN: DiffLogic resolved the differentiable training challenge of LGNs, and CLGN introduced convolutional logic layers to capture spatial structures, but both target classification tasks. LogicIR's core contribution lies in adapting the LGN paradigm to pixel-level dense prediction tasks, utilizing bit decoding (mapping binary outputs to continuous pixels) and a UNet architecture (addressing hierarchical representation and multi-scale fusion). This shows that the bottleneck for shifting LGNs from classification to dense prediction lies in output reconstruction rather than feature extraction.
vs BBCU / Bi-Real (BNN Route): BNN methods still need to retain partial full-precision layers (input and output layers) and full-precision adders in residual connections, which is essentially incomplete discretization. LogicIR's 'pure logic' route has a qualitative difference in hardware friendliness—it proves that high-quality image restoration is still achievable after completely removing weight storage and arithmetic operations. The insight for BNN research is: instead of incrementally binarizing more layers, it is better to directly transition to the pure logic gate paradigm.
vs HKLUT / MuLUT (LUT Route): The fundamental contradiction of LUT methods lies in the exponential trade-off between receptive field and memory. LogicIR can essentially be viewed as a 'differentiable self-adaptive LUT'—the tree structures of logic kernels naturally encode small-range input-output mappings (similar to LUTs), but break the receptive field ceiling of individual LUTs via hierarchical stacking and multi-layer combinations. This suggests there might be a deeper unified perspective linking LUTs and LGNs.
vs ShuffleNet: The channel rotation mechanism of Index Shuffling is directly inspired by the channel shuffle concept of ShuffleNet, but is applied to a different scenario—in ShuffleNet, shuffle is used to mix channel information after grouped convolutions, while in LogicIR, it is used to break the group isolation of randomly fixed connections. This cross-domain transfer (from CNN architecture design to logic gate network connection pattern design) illustrates that good design patterns can transcend computing paradigms.

Rating¶

Novelty: 4/5 — This work introduces the LGN paradigm to image restoration for the first time. The bit decoding and Index Shuffling components are innovative, though the UNet wrapper is relatively standard. Overall, the contribution lies in expanding to a challenging application area rather than presenting an entirely raw paradigm.
Experimental Thoroughness: 4/5 — The experiments cover three core image restoration tasks with complete component ablations, grouped connection analysis, and color-processing comparisons. The hardware implementation on physical FPGAs (measuring latency, energy, and area) is a substantial plus; of note, direct comparisons with other generic network compression methods (e.g., pruning, knowledge distillation) are limited.
Writing Quality: 4/5 — The paper presents a highly structured narrative with logical development. Motivation comparisons with BNNs and LUTs are clear, and the method components are well-detailed. Convincing qualitative visualizations (feature maps, trade-off bubbles) are provided, though certain hyperparameter and rotation-augmented training details are left to the supplemental materials.
Value: 4/5 — It provides an established baseline and framework for using pure discrete logic computation for dense pixel-level prediction, offering substantial value for edge deployment of low-level visual tasks. The FPGA results support the claims on computational efficiency, though extending to upsampling tasks (like super-resolution) remains the critical bottleneck for its long-term impact.